1. Field of the Invention
The invention relates to a semiconductor device and more specifically to a multi-chip package device.
2. Description of the Related Art
In recent years, the demand has sharply increased for portable electronic equipment, such as mobile phones, portable information processing terminals, small-sized music players, etc.
To meet the demand, attempts have been made to miniaturize semiconductor devices.
Accordingly, a System On Chip (SOC) technology to build two or more systems into one semiconductor chip and a multi-chip package (MCP) technology to stack two or more semiconductor chips on one package board have been used in semiconductor devices.
The SOC technology is one by which two or more systems are packaged together in one semiconductor chip. In contrast, the MCP technology is one by which two or more semiconductor chips are incorporated into one package.
With the MCP technology, miniaturization can be effected by contriving a method to stack two or more semiconductor chips (see, for example, JP-A No. 2005-286126 (KOKAI)).
In the structure of an MCP device, wire bonding is used to connect the input/output pads of semiconductor chips to the pads of a package board. Thus, an appropriate space for wire bonding is required in the vicinity of the pads of semiconductor chips.
To this end, a spacer is placed between two semiconductor chips to be stacked, thereby securing a space for wire bonding.
However, the use of a spacer results in an increase in the size in the direction of the thickness of the MCP device.
In addition, as the number of semiconductor chips to be stacked on the package board increases, the number of pads and wires also increases. In such a case, connection between the package board and the semiconductor chips becomes complicated, which can cause short-circuiting of wires. Furthermore, it is intricate to lead board interconnections on the package board.